Feature Descriptions; Zynq-7000 Xc7Z045 Ap Soc - Xilinx ZC706 User Manual

Feature Descriptions

Detailed information for each feature shown in
provided in this section.

Zynq-7000 XC7Z045 AP SoC

[Figure 1-2, callout 1]
The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C AP SoC.
The XC7Z045 AP SoC consists of an integrated processing system (PS) and programmable
logic (PL), on a single die. The high-level block diagram is shown in
X-Ref Target - Figure 1-3
Processing
Input Output
Peripherals
High-Bandwidth
®
AMBA
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA®
interconnect, internal memories, external memory interfaces, and peripherals including
USB, Ethernet, SPI, SD/SDIO,
and boots at power-up or reset.
A system level block diagram is shown in
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
System
(PS)
(IOP)
AXI Interfaces
Common Accelerators
Figure 1-3: High-Level Block Diagram
, CAN, UART, and GPIO. The PS runs independently of the PL
2
I C
www.xilinx.com
Figure 1-2 and listed in
Memory
Interfaces
Application
Processor Unit (APU)
Interconnect
Custom Accelerators
Figure 1-4.
Feature Descriptions
Table 1-1 is
Figure 1-3.
Programmable
Logic
(PL)
Common
Peripherals
Custom
Peripherals
UG954_c1_03_100112
14
Send Feedback