Xilinx ZC706 User Manual page 45

Table 1-17 lists the GTX Bank 112 interface connections between the AP SoC U1 and PCIe
4-lane connector P4.
Table 1-16: AP SoC GTX Bank 112 Interface Connections to PCIe 4-Lane Connector P4
Transceiver AP SoC U1 Pin
Bank
GTX_BANK_112 T2
T1
V6
V5
R4
R3
U4
U3
P2
P1
T6
T5
N4
N3
P6
P5
N8
N7
R8
R7
Notes:
1. PCIE_TXn_P/N and PCIE_CLK_Q0_P/N are capacitively coupled to the PCIe edge connector P4.
For additional information about Zynq-7000 PCIe functionality, see 7 Series FPGAs
Integrated Block for PCI Express Product Guide for Vivado Design Suite (
information about the PCI Express standard is available
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
AP SoC U1 Pin Name Schematic Net Name
Number
MGTPTXP0_112
MGTPTXN0_112
MGTPRXP0_112
MGTPRXN0_112
MGTPTXP1_112
MGTPTXN1_112
MGTPRXP1_112
MGTPRXN1_112
MGTPTXP2_112
MGTPTXN2_112
MGTPRXP2_112
MGTPRXN2_112
MGTPTXP3_112
MGTPTXN3_112
MGTPRXP3_112
MGTPRXN3_112
MGTREFCLK0P_112
MGTREFCLK0N_112
MGTREFCLK1P_112
MGTREFCLK1N_112
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Feature Descriptions
PCIe 4-Lane Conn. P4
PCIE_TX3_P A29 (1)
PCIE_TX3_N A30 (1)
PCIE_RX3_P B27
PCIE_RX3_N B28
PCIE_TX2_P A25 (1)
PCIE_TX2_N A26 (1)
PCIE_RX2_P B23
PCIE_RX2_N B24
PCIE_TX1_P A21 (1)
PCIE_TX1_N A22 (1)
PCIE_RX1_P B19
PCIE_RX1_N B20
PCIE_TX0_P A16 (1)
PCIE_TX0_N A17 (1)
PCIE_RX0_P B14
PCIE_RX0_N B15
PCIE_CLK_QO_P A13 (1)
PCIE_CLK_QO_N A14 (1)
NC NA
NC NA
PG054
[Ref 22].
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