Xilinx ZC706 User Manual page 43

Table 1-15 lists the GTX Bank interface connections between the AP SoC U1 and FMC LPC
connector J5.
Table 1-15: AP SoC GTX Bank 111 Interface Connections to FMC LPC J5
AP SoC U1
Transceiver
Pin
Bank
Number
AB2
AB1
AC4
AC3
Y2
Y1
AB6
AB5
W4
W3
GTX_BANK_11
1
Y6
Y5
V2
V1
AA4
AA3
U8
U7
W8
W7
Notes:
1. AP SoC U1 GTX input clock nets are capacitively coupled to the FMC LPC J5 pins.
2. AP SoC U1 GTX input nets are capacitively coupled to the RX and MGT_REFCLK SMA pins.
For additional information on Zynq-7000 GTX transceivers, see 7 Series FPGAs GTX/GTH
Transceivers User Guide (UG476).
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
AP SoC U1 Pin
Name
MGTPTXP0_111 FMC_LPC_DP0_C2M_P
MGTPTXN0_111 FMC_LPC_DP0_C2M_N
MGTPRXP0_111 FMC_LPC_DP0_M2C_P
MGTPRXN0_111 FMC_LPC_DP0_M2C_N
MGTPTXP1_111 SMA_MGT_TX_P
MGTPTXN1_111 SMA_MGT_TX_N
MGTPRXP1_111 SMA_MGT_RX_P
MGTPRXN1_111 SMA_MGT_RX_N
MGTPTXP2_111 SFP_TX_P
MGTPTXN2_111 SFP_TX_N
MGTPRXP2_111 SFP_RX_P
MGTPRXN2_111 SFP_RX_N
MGTPTXP3_111 (capacitively coupled to AA4)
MGTPTXN3_111 (Cooperatively coupled to AA3)
MGTPRXP3_111 See Pin V2 loopback
MGTPRXN3_111 See Pin V1 loopback
MGTREFCLK0P_111 FMC_LPC_GBTCLK0_M2C_C_P
MGTREFCLK0N_111 FMC_LPC_GBTCLK0_M2C_C_N
MGTREFCLK1P_111 SMA_MGT_REFCLK_P
MGTREFCLK1N_111 SMA_MGT_REFCLK_N
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Schematic Net Name
(2)
(2)
(1)
(1)
(2)
(2)
Feature Descriptions
Connected Connected
Pin Device
C2
C3
FMC LPC
J5
C6
C7
J35.1
J34.1
GTX TX/RX
SMA
J32.1
J33.1
18
19
SFP+
Conn. P2
13
12
U1.AA4
AP SoC U1
U1.AA3
GTX
U1.V2
Loopback
U1.V1
D4
FMC LPC
J5
D5
J36.1 GTX
REFCLK
J31.1
SMA
43
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