Encryption Key Backup Circuit - Xilinx ZC706 User Manual

• PL Configuration: USB JTAG configuration port (Digilent module U30)
• PL Configuration: Platform cable header J3 and flying lead header J62 JTAG
configuration ports
Designs using serial configuration based on Quad-SPI flash memory can take advantage of
TIP:
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW11 (PS) as shown in
SW4 (PL) as described in
is callout 29 in
Table 1-2: Switch SW11 Configuration Option Settings
Boot Mode
(1)
JTAG mode
Independent JTAG mode
QSPI mode
SD mode
MIO configuration pin
Notes:
1. Default switch setting
For more information about Zynq-7000 AP SoC configuration settings, see Zynq-7000 All
Programmable SoC Technical Reference Manual (UG585).

Encryption Key Backup Circuit

The XC7Z045 AP SoC U1 implements bitstream encryption key technology. The ZC706
board provides the encryption key backup battery circuit shown in
TS518FE rechargeable 1.5V lithium button-type battery B2 is soldered to the board with the
positive output connected to the XC7Z045 AP SoC U1 VCCBATT pin P9. The battery supply
current IBATT specification is 150 nA max when board power is off. B2 is charged from the
VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and
4.7 K Ω current limit resistor. The nominal charging voltage is 1.42V.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Programmable Logic JTAG Programming Options, page
Figure 1-2.
www.xilinx.com
SW11.1 SW11.2 SW11.3
0 0
1 0
0 0
0 0
MIO2 MIO3
Feature Descriptions
Table 1-2
31. SW11
SW11.4 SW11.5
0 0
0 0
0 1
1 1
MIO4 MIO5 MIO6
Figure 1-5. The Seiko
Send Feedback
and
0
0
0
0
16