Powerpc™ 405 Core; Rocketio 3.125 Gb/S Transceivers - Xilinx ML310 User Manual

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Table 1-1: Virtex-II Pro Family Members
Device 2VP2
Logic Cells 3,168
PPC405 0
MGTs 4
BRAM 216
(Kbits)
Xtreme 12
Multipliers
PowerPC™ 405 Core
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RocketIO 3.125 Gb/s Transceivers

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12
2VP4 2VP7 2VP20
6,768 11,088 20,880
1 1 2
4 8 8
504 792 1,584
28 44 88
Embedded 300+ MHz Harvard architecture core
Low power consumption: 0.9 mW/MHz
Five-stage data path pipeline
Hardware multiply/divide unit
Thirty-two 32-bit general purpose registers
16 KB two-way set-associative instruction cache
16 KB two-way set-associative data cache
Memory Management Unit (MMU)
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64-entry unified Translation Look-aside Buffers (TLB)
♦
Variable page sizes (1 KB to 16 MB)
Dedicated on-chip memory (OCM) interface
Supports IBM CoreConnect™ bus architecture
Debug and trace support
Timer facilities
Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s
to 3.125 Gb/s
80 Gb/s duplex data rate (16 channels)
Monolithic clock synthesis and clock recovery (CDR)
Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and
Infiniband-compliant transceivers
8-, 16-, or 32-bit selectable internal FPGA interface
8B /10B encoder and decoder
50Ω/75Ω on-chip selectable transmit and receive terminations
Programmable comma detection
Channel bonding support (two to sixteen channels)
Rate matching via insertion/deletion characters
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Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK
2VP30 2VP40 2VP50
30,816 43,632 53,136
2 2 2
8 12 16
2,448 3,456 4,176
136 192 232
2VP70 2VP100 2VP125
74,448 99,216 125,136
2 2 4
20 20 24
5,904 7,992 10,008
328 444 556
ML310 User Guide
UG068 (v1.01) August 25, 2004