Xilinx ZC706 User Manual page 28

The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in
Table 1-8.
Table 1-8: USB Connector Pin Assignments and Signal Definitions Between J2 and U12
USB Connector
J1
Pin Name
1 VBUS USB_VBUS_SEL
2 D_N USB_D_N
3 D_P USB_D_P
5 GND GND
The connections between the USB 2.0 PHY at U12 and the XC7Z045 AP SoC are listed in
Table 1-9.
Table 1-9: USB 2.0 ULPI Transceiver Connections to the XC7Z045 AP SoC
XC7Z045 (U1)
Pin Name Bank
PS_MIO36 501
PS_MIO31 501
PS_MIO32 501
PS_MIO33 501
PS_MIO34 501
PS_MIO35 501
PS_MIO28 501
PS_MIO37 501
PS_MIO38 501
PS_MIO39 501
PS_MIO30 501
PS_MIO29 501
PS_MIO7 500
For additional information on the Zynq-7000 AP SoC device USB controllers, see Zynq-7000
All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC Technical
Reference Manual (UG585).
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Net Name
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
Pin Number
H17
H21
K17
G22
K18
G21
L17
B21
A20
F18
L18
E8
D5
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Description
Schematic Net Name
USB_CLKOUT
USB_NXT
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
USB_STP
USB_DIR
USB_RESET_B_AND
Feature Descriptions
USB3320 (U12)
Pin
22
19
18
33
USB3320 (U12) Pin
1
2
3
4
5
6
7
9
10
13
29
31
27 (via AND gate U13)
28
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