Gtp Transceivers - Xilinx AC701 User Manual

GTP Transceivers

[Figure
The AC701 board provides access to 8 GTP transceivers:
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The GTP transceivers in 7 series FPGAs are grouped into four channels described as
Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below
the GTP Quad of interest. There are two GTP Quads on the AC701 board with connectivity
as shown here:
•
•
Table 1-12
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
1-2, callout 11]
Four of the GTP transceivers are wired to the PCI Express® x4 endpoint edge
connector (P1) fingers
Two of the GTP transceivers are wired to the FMC HPC connector (J30)
One GTP is wired to SMA connectors (RX: J46, J47 TX: J44, J45)
One GTP is wired to the SFP/SFP+ Module connector (P3)
Quad 213
• Contains 4 GTP transceivers:
- GTP0 SFP
- GTP1 FMC HPC DP0
- GTP2 FMC HPC DP1
GTP3 SMA TX/RX Connector Pairs
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• MGTREFCLK0 Clock Mux U3 output
• MGTREFCLK1 Clock Mux U4 output
Quad 216
• Contains 4 GTP transceivers for PCIe lanes 0-3
• MGTREFCLK0 PCIe edge connector clock
• MGTREFCLK1 NC
lists the GTP interface connections to the FPGA (U1).
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