Xilinx ZC706 User Manual page 104

set_property PACKAGE_PIN B5 [get_ports PL_DDR3_D27]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D27]
set_property PACKAGE_PIN A3 [get_ports PL_DDR3_D28]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D28]
set_property PACKAGE_PIN B1 [get_ports PL_DDR3_D29]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D29]
set_property PACKAGE_PIN C1 [get_ports PL_DDR3_D30]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D30]
set_property PACKAGE_PIN C4 [get_ports PL_DDR3_D31]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D31]
set_property PACKAGE_PIN K10 [get_ports PL_DDR3_D32]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D32]
set_property PACKAGE_PIN L9 [get_ports PL_DDR3_D33]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D33]
set_property PACKAGE_PIN K12 [get_ports PL_DDR3_D34]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D34]
set_property PACKAGE_PIN J9 [get_ports PL_DDR3_D35]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D35]
set_property PACKAGE_PIN K11 [get_ports PL_DDR3_D36]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D36]
set_property PACKAGE_PIN L10 [get_ports PL_DDR3_D37]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D37]
set_property PACKAGE_PIN J10 [get_ports PL_DDR3_D38]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D38]
set_property PACKAGE_PIN L7 [get_ports PL_DDR3_D39]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D39]
set_property PACKAGE_PIN F14 [get_ports PL_DDR3_D40]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D40]
set_property PACKAGE_PIN F15 [get_ports PL_DDR3_D41]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D41]
set_property PACKAGE_PIN F13 [get_ports PL_DDR3_D42]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D42]
set_property PACKAGE_PIN G16 [get_ports PL_DDR3_D43]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D43]
set_property PACKAGE_PIN G15 [get_ports PL_DDR3_D44]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D44]
set_property PACKAGE_PIN E12 [get_ports PL_DDR3_D45]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D45]
set_property PACKAGE_PIN D13 [get_ports PL_DDR3_D46]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D46]
set_property PACKAGE_PIN E13 [get_ports PL_DDR3_D47]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D47]
set_property PACKAGE_PIN D15 [get_ports PL_DDR3_D48]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D48]
set_property PACKAGE_PIN E15 [get_ports PL_DDR3_D49]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D49]
set_property PACKAGE_PIN D16 [get_ports PL_DDR3_D50]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D50]
set_property PACKAGE_PIN E16 [get_ports PL_DDR3_D51]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D51]
set_property PACKAGE_PIN C17 [get_ports PL_DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D52]
set_property PACKAGE_PIN B16 [get_ports PL_DDR3_D53]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D53]
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
www.xilinx.com
ZC706 Evaluation Board XDC Listing
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