Xilinx ZC706 User Manual page 41

Table 1-14 lists the GTX Banks 109 and 110 interface connections between the AP SoC U1
and FMC HPC connector J37.
Table 1-14: AP SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37
AP SoC U1
Transceiver
Pin
Bank
Number
AK10
AK9
AH10
AH9
AK6
AK5
AJ8
AJ7
AJ4
AJ3
GTX_BANK_109
AG8
AG7
AK2
AK1
AE8
AE7
AD10
AD9
AF10
AF9
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
AP SoC U1 Pin Name
MGTPTXP0_109 FMC_HPC_DP0_C2M_P
MGTPTXN0_109 FMC_HPC_DP0_C2M_N
MGTPRXP0_109 FMC_HPC_DP0_M2C_P
MGTPRXN0_109 FMC_HPC_DP0_M2C_N
MGTPTXP1_109 FMC_HPC_DP1_C2M_P
MGTPTXN1_109 FMC_HPC_DP1_C2M_N
MGTPRXP1_109 FMC_HPC_DP1_M2C_P
MGTPRXN1_109 FMC_HPC_DP1_M2C_N
MGTPTXP2_109 FMC_HPC_DP2_C2M_P
MGTPTXN2_109 FMC_HPC_DP2_C2M_N
MGTPRXP2_109 FMC_HPC_DP2_M2C_P
MGTPRXN2_109 FMC_HPC_DP2_M2C_N
MGTPTXP3_109 FMC_HPC_DP3_C2M_P
MGTPTXN3_109 FMC_HPC_DP3_C2M_N
MGTPRXP3_109 FMC_HPC_DP3_M2C_P
MGTPRXN3_109 FMC_HPC_DP3_M2C_N
MGTREFCLK0P_109 FMC_HPC_GBTCLK0_M2C_C_P
MGTREFCLK0N_109 FMC_HPC_GBTCLK0_M2C_C_N
MGTREFCLK1P_109 NC
MGTREFCLK1N_109 NC
www.xilinx.com
Schematic Net Name
(1)
(1)
Feature Descriptions
Connected Connected
Pin Device
C2
C3
C6
C7
A22
A23
A2
A3
A26
FMC HPC
J37
A27
A6
A7
A30
A31
A10
A11
D4
D5
NA NA
NA NA
41
Send Feedback