Block Diagram; Board Layout - Xilinx ZC706 User Manual

Block Diagram

The ZC706 evaluation board block diagram is shown in
X-Ref Target - Figure 1-1
Dual Quad-SPI
Flash Memory
Page 21
PCIe
x 4-Lane
Page 42
SD Card
Connector
Page 22
FMC HPC
Connector
Pages 24-27
FMC LPC
Connector
Page 28
Mechanicals 10/100/1,000
Ethernet PHY
(RGMII only)
Page 58 Page 29, 30
Note: Page numbers reference the page number of schematic 0381513.

Board Layout

Figure 1-2 shows the ZC706 evaluation board. Each numbered feature that is referenced in
Figure 1-2 is described in
Feature Descriptions
The image in
Note:
board.
The ZC706 evaluation board can be damaged by electrostatic discharge (ESD). Follow ESD
CAUTION!
prevention measures when handling the board.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
JTAG Module DDR3 Memory
and 4 x 256 Mb x 8
JTAG Header SDRAM
Page 16 Pages 17-20
Processing
System
U1
Zync-7000 AP SoC
XC7Z045-2FFG900C
Programmable Logic
USB 2.0 ULPI HDMI Codec
Transceiver and
and Connector Connector
Page 31 Pages 32, 33
Figure 1-1: ZC706 Evaluation Board Block Diagram
Table 1-1 with a link to detailed information provided under
starting on page 14.
Figure 1-2 is for reference only and might not reflect the current revision of the
www.xilinx.com
Figure 1-1.
DDR3 Clock and
SODIMM Reset/POR
Pushbuttons
Page 23 Pages 15, 34
Configurable XADC
Clocks Header
Page 34 Page 35
Overview
USB UART
and
Connector
Page 40
ARM PJTAG
Header
Page 39
Switches
LEDs and
Pushbuttons
Page 38
2
I C
Real Time
Clock
Page 37
2
I C Multiplexer
and
2
I C EEPROM
Page 36
UG954_c1_01_1002012
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