Jumpers - Xilinx ZC706 User Manual

Jumpers

[Figure 1-2, callout 24]
Default jumper positions are listed in
Table A-2: Default Jumper Settings
Jumper
Jumper
Callout
1 J6 AP SoC U1 Bank 0 CFGBVS pin V9 logic 0/1 Select
(call out #1 applies to this, too):
J65 J65 is an INIT_B (pin 1) and DONE (pin 2) test
header
2 J7 U8 MAX16025 POR Device Reset MR_B pin 13 logic
0/1 Select
3 J8 JTAG Header J62 pin 2 can be connected to 3.3V
4 J9 U51 Ethernet PHY CONFIG2 pin 2 1K pull-down to
logic 0 (GND)
5 J10 U12 USB3320 2.0 Host/OTG or Device Select
Header
6 J11 U12 USB3320 2.0 RESET Header
7 J12 U38 REF3012 VREF XADC_AGND-to-GND L3
inductor bypass
8 J13 U38 REF3012 VREF XADC_AGND-to-GND Select
Header
9 J14 XADC circuit VCC5V0 sources XADC_VCC5V0 Select
Header
10 J15 ARM PJTAG Header J64 pin 2 can be connected to
VADJ
11 J17 SPF+ P2 pin 3 SFP_TX_DISABLE_TRANS logic 0/1
Select Header
12 J18 FMC_VADJ_ON_B Select Header
13 J19 PCIe® Lane Width Select Header
14 J66 PL_PWR_ON Header
15 J69 XADC Power System Vccint CS OpAmp U69 Gain
Select Header
16 J70 MIO Select Header MIO2 (Note: DIP SW11 pole 1
affects this signal)
17 J71 MIO Select Header MIO3 (Note: DIP SW11 pole 2
affects this signal)
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Table A-2.
Function
HDR_1 X 2
www.xilinx.com
Default Jumper
Option Selected
Position
OPEN CFGBVS pin V9 = 1
OPEN N/A
OPEN U8 MR_B pin 13 = 1
OPEN J62 pin 2 is NC
1-2 U51 pin 2 CONFIG2 = 0
1-2 HOST source VBUS power
(from U22)
OPEN U12 not held in RESET
OPEN L3 not bypassed
1-2 XADC_AGND connected to
GND
1-2 XADC_VCC5V0 = filtered
(L1) VCC5V0
OPEN J64 pin 2 is NC
OPEN SPF+ P2 SFP TX is enabled
(P2 pin 3 = 1)
1-2 FMC VADJ enabled (U48
UCD90120A pin 37 = logic
0)
3-4 4-Lane PCIe selected
OPEN PL Power enabled
(U48 UCD90120A pin 24 =
logic 1)
OPEN U69 Current Sense OpAmp
Gain = 10
1-2 QSPI0_IO0 = MIO2_SELECT
1-2 QSPI0_IO1 = MIO3_SELECT
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Jumpers
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