Xilinx ZC706 User Manual page 21

Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont'd)
XC7Z045 (U1)
Pin
B11
C14
B14
J3
F2
E1
C2
L12
G14
C16
C11
K2
K3
H1
J1
D5
E6
A4
A5
K8
L8
F12
G12
E17
F17
A15
B15
G7
C9
G17
J11
H8
M10
F7
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Net Name I/O Standard
PL_DDR3_D61
PL_DDR3_D62
PL_DDR3_D63
PL_DDR3_DM0
PL_DDR3_DM1
PL_DDR3_DM2
PL_DDR3_DM3
PL_DDR3_DM4
PL_DDR3_DM5
PL_DDR3_DM6
PL_DDR3_DM7
PL_DDR3_DQS0_N DIFF_SSTL15
PL_DDR3_DQS0_P DIFF_SSTL15
PL_DDR3_DQS1_N DIFF_SSTL15
PL_DDR3_DQS1_P DIFF_SSTL15
PL_DDR3_DQS2_N DIFF_SSTL15
PL_DDR3_DQS2_P DIFF_SSTL15
PL_DDR3_DQS3_N DIFF_SSTL15
PL_DDR3_DQS3_P DIFF_SSTL15
PL_DDR3_DQS4_N DIFF_SSTL15
PL_DDR3_DQS4_P DIFF_SSTL15
PL_DDR3_DQS5_N DIFF_SSTL15
PL_DDR3_DQS5_P DIFF_SSTL15
PL_DDR3_DQS6_N DIFF_SSTL15
PL_DDR3_DQS6_P DIFF_SSTL15
PL_DDR3_DQS7_N DIFF_SSTL15
PL_DDR3_DQS7_P DIFF_SSTL15
PL_DDR3_ODT0
PL_DDR3_ODT1
PL_DDR3_RESET_B
PL_DDR3_S0_B
PL_DDR3_S1_B
PL_DDR3_TEMP_EVE
NT
PL_DDR3_WE_B
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DDR3 SODIMM Memory J1
Pin Number
SSTL15 182
SSTL15 192
SSTL15 194
SSTL15 11
SSTL15 28
SSTL15 46
SSTL15 63
SSTL15 136
SSTL15 153
SSTL15 170
SSTL15 187
10
12
27
29
45
47
62
64
135
137
152
154
169
171
186
188
SSTL15 116
SSTL15 120
SSTL15 30
SSTL15 114
SSTL15 121
SSTL15 198
SSTL15 113
Feature Descriptions
Pin Name
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0_N
DQS0_P
DQS1_N
DQS1_P
DQS2_N
DQS2_P
DQS3_N
DQS3_P
DQS4_N
DQS4_P
DQS5_N
DQS5_P
DQS6_N
DQS6_P
DQS7_N
DQS7_P
ODT0
ODT1
RESET_B
S0_B
S1_B
EVENT_B
WE_B
21
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