Xilinx ZC706 User Manual page 105

set_property PACKAGE_PIN D14 [get_ports PL_DDR3_D54]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D54]
set_property PACKAGE_PIN B17 [get_ports PL_DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D55]
set_property PACKAGE_PIN B12 [get_ports PL_DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D56]
set_property PACKAGE_PIN C12 [get_ports PL_DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D57]
set_property PACKAGE_PIN A12 [get_ports PL_DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D58]
set_property PACKAGE_PIN A14 [get_ports PL_DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D59]
set_property PACKAGE_PIN A13 [get_ports PL_DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D60]
set_property PACKAGE_PIN B11 [get_ports PL_DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D61]
set_property PACKAGE_PIN C14 [get_ports PL_DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D62]
set_property PACKAGE_PIN B14 [get_ports PL_DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_D63]
set_property PACKAGE_PIN J3 [get_ports PL_DDR3_DM0]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM0]
set_property PACKAGE_PIN F2 [get_ports PL_DDR3_DM1]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM1]
set_property PACKAGE_PIN E1 [get_ports PL_DDR3_DM2]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM2]
set_property PACKAGE_PIN C2 [get_ports PL_DDR3_DM3]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM3]
set_property PACKAGE_PIN L12 [get_ports PL_DDR3_DM4]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM4]
set_property PACKAGE_PIN G14 [get_ports PL_DDR3_DM5]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM5]
set_property PACKAGE_PIN C16 [get_ports PL_DDR3_DM6]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM6]
set_property PACKAGE_PIN C11 [get_ports PL_DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_DM7]
set_property PACKAGE_PIN K2 [get_ports PL_DDR3_DQS0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS0_N]
set_property PACKAGE_PIN K3 [get_ports PL_DDR3_DQS0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS0_P]
set_property PACKAGE_PIN H1 [get_ports PL_DDR3_DQS1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS1_N]
set_property PACKAGE_PIN J1 [get_ports PL_DDR3_DQS1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS1_P]
set_property PACKAGE_PIN D5 [get_ports PL_DDR3_DQS2_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS2_N]
set_property PACKAGE_PIN E6 [get_ports PL_DDR3_DQS2_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS2_P]
set_property PACKAGE_PIN A4 [get_ports PL_DDR3_DQS3_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS3_N]
set_property PACKAGE_PIN A5 [get_ports PL_DDR3_DQS3_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS3_P]
set_property PACKAGE_PIN K8 [get_ports PL_DDR3_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS4_N]
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
www.xilinx.com
ZC706 Evaluation Board XDC Listing
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