I2C Bus - Xilinx ZC706 User Manual

Table 1-24 lists the connections between the codec and the HDMI receptacle P1.
Table 1-24: ADV7511 to HDMI Receptacle Connections
ADV7511 (U53)
36
35
40
39
43
42
33
32
54
53
52
51
48
Information about the ADV7511KSTZ-P is available on the Analog Devices website
For additional information about HDMI IP options, see the LogiCORE IP DisplayPort Product
Guide for Vivado Design Suite (PG064).

I2C Bus

[Figure 1-2, callout 20]
The ZC706 evaluation board implements two
port (IIC_SDA and _SCL_MAIN) is routed to level shifter U87. The PS-side
2
I C
(PS_SDA and _SCL_MAIN) is routed to level shifter U88. The "output" side of the two level
shifters are wired to the common
Semiconductor PCA9548 1-to-8 channel
at speeds up to 400 kHz.
The PCA9548 U65 RESET_B pin 24 is connected to FPGA U1 bank 501 pin F20 via
IMPORTANT:
level-shifter U25. FPGA pin F20 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus
transactions with the devices connected to U65.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
HDMI Receptacle
Net Name
P1 Pin
HDMI_D0_P
HDMI_D0_N
HDMI_D1_P
HDMI_D1_N
HDMI_D2_P
HDMI_D2_N
HDMI_CLK_P
HDMI_CLK_N
HDMI_DDCSDA
HDMI_DDCSCL
HDMI_HEAC_P
HDMI_HEAC_N
HDMI_CEC
bus IIC_SDA and _SCL_MAIN which is connected to TI
2
I C
2
I
www.xilinx.com
7
9
4
6
1
3
10
12
16
15
14
19
13
ports on the XC7Z045 AP SoC. The PL-side
2
I C
bus switch (U65). The bus switch can operated
C
Feature Descriptions
[Ref 25].
port
2
I C
53
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