Xilinx ZC706 User Manual page 32

X-Ref Target - Figure 1-10
14PIN_JTAG_TDI
To J3
14PIN_JTAG_TMS
Parallel Cable or
Platform Cable
(14 pins) 14PIN_JTAG_TCK
DIGILENT_TDI
To U30
DIGILENT_TMS
USB-to-JTAG
Digilent bridge
DIGILENT_TCK
20PIN_JTAG_TDI
To J62
20PIN_JTAG_TMS
Parallel Cable
(20 Pins)
20PIN_JTAG_TCK
Figure 1-10: PL JTAG Programming Source Analog Switch
DIP switch SW4[1:2] setting 10 selects the 14-pin header J3 for configuration using either a
Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW4 setting 01 selects the
USB-to-JTAG Digilent bridge U30 for configuration over a Standard-A to Micro-B USB cable.
DIP switch SW4 setting 11 selects the JTAG 20-pin header at J62. The four JTAG signals TDI,
TDO, TCK, and TMS would be connected to J62 through flying leads from a JTAG cable. The
3-to-1 analog switch settings are shown in
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
U45
VCC3V3
TS5A3359
SP3T
ANALOG SWITCH
6
IN1
5
IN2
1
NO0
2 7
NO1 COM
3
NO2
4 8
GND V+
U46
TS5A3359
SP3T
ANALOG SWITCH
6
IN1
5
IN2
1
NO0
2 7
NO1
COM
3
NO2
4 8
GND V+
U47
TS5A3359
SP3T
ANALOG SWITCH
6
IN1
5
IN2
1 NO0
2 NO1 7
COM
3 NO2
4 8
GND V+
Table 1-11.
www.xilinx.com
Feature Descriptions
VCC3V3
4 3
SW4
SDA02H1SBD
1 2
JTAG_SEL_1
JTAG_SEL_2
R21
4.7kΩ
0.1 W
5%
R20
4.7kΩ
0.1 W
5%
GND
JTAG_TMS
JTAG_TCK
UG954_c1_10_041113
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JTAG_TDI
32