10/100/1000 Mb/S Tri-Speed Ethernet Phy (Pl) - Xilinx ZC706 User Manual

Table 1-17: AP SoC U1 to SFP+ Module Connections
AP SoC (U1) Pin
Y5
Y6
W4
W3
AA18
Table 1-18 lists the SFP+ module control and status connections to the AP SoC.
Table 1-18: SFP+ Module Control and Status Connections
SFP Control/ Status
Signal
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
SFP_LOS
For additional information about the enhanced Small Form Factor Pluggable (SFP+)
module, see the SFF-8431 specification

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PL)

[Figure 1-2, callout 15]
The ZC706 evaluation board uses the Marvell Alaska PHY device (88E1116R) at U51 for
Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII
mode only. The PHY connection to a user-provided Ethernet cable is through a Halo
HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY
address 0b00111 using the settings shown in
via software commands passed over the MDIO interface.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Schematic Net name
SFP_RX_N
SFP_RX_P
SFP_TX_P
SFP_TX_N
SFP_TX_DISABLE_TRANS
Board Connection
Test Point J23
Low = Normal operation
Jumper 17
High = Module not present
Test Point J24
Jumper pins 1-2 = Full RX bandwidth
Jumper 56
Jumper pins 2-3 = Reduced RX bandwidth
Jumper pins 1-2 = Full TX bandwidth
Jumper 55
Jumper pins 2-3 = Reduced TX bandwidth
High = Loss of receiver signal
Test Point J25
Low = Normal operation
[Ref
www.xilinx.com
SFP+ Module (P2)
Pin
12
13
18
19
3
High = Fault
Off = SFP Disabled
On = SFP enabled
Low = Module present
23].
Table 1-19. These settings can be overwritten
Feature Descriptions
Name
RD_N
RD_P
TD_P
TD_N
TX_DISABLE
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