Jitter Attenuated Clock - Xilinx ZC706 User Manual

Figure 1-15 shows this AC-coupled clock circuit.
X-Ref Target - Figure 1-15

Jitter Attenuated Clock

[Figure 1-2, callout 11]
The ZC706 board includes a Silicon Labs Si5324 jitter attenuator U60 on the back side of the
board. AP SoC user logic can implement a clock recovery circuit and then output this clock
to a differential I/O pair on I/O bank 9 (REC_CLOCK_C_P, AP SoC U1 pin AD20 and
REC_CLOCK_C_N, AP SoC U1 pin AE20) for jitter attenuation. The jitter attenuated clock
(Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTX Quad 110
inputs MGTREFCLK1P (AP SoC U1 pin AC8) and MGTREFCLK1N (AP SoC U1 pin AC7).
The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock
recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered
clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock
circuit is shown in
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
J36
SMA_MGT_REFCLK_C_P
SMA
Connector
J31
GND
SMA_MGT_REFCLK_C_N
SMA
Connector
GND
Figure 1-15: GTX SMA Clock Source
Figure 1-16.
www.xilinx.com
C145
SMA_MGT_REFCLK_P
0.01 μF 25V
X7R
C144
SMA_MGT_REFCLK_N
0.01 μF 25V
X7R
UG954_c1_15_041113
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