Xilinx ZC706 User Manual page 54

The ZC706 evaluation board
X-Ref Target - Figure 1-22
U1
XC7Z045 AP SoC
PL Bank 10
(2.5V)
IIC_SCL/SDA_MAIN
U1
XC7Z045 AP SoC
PS Bank 501
(1.8V)
PS_SDA/SCL_MAIN
User applications that communicate with devices on one of the downstream I
first set up a path to the desired bus through the U65 bus switch at I
(0b01110100).
2
Table 1-25: I C Bus Addresses
Device
PCA9548 8-Channel bus switch
Si570 clock
ADV7511 HDMI
I2C EEPROM
I2C port expander and
DDR3 SODIMM
I2C real time clock and
Si5324 clock
FMC HPC
FMC LPC
UCD90120A pmbus
Information about the PCA9548 is available on the TI Semiconductor website at
For additional information on the Zynq-7000 AP SoC device I
All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC Technical
Reference Manual (UG585).
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
bus topology is shown in
2
I C
VADJ 2.5V 3.3 V
U87
PCA9517
2
I C
Level Shifter
A B
3.3 V
VCCMIO_PS 1.8V
U88
PCA9517
2
I C
Level Shifter
A B
Figure 1-22: I
Table 1-25 lists the address for each bus.
2
I C Switch Position
NA
0
1
2
3
4
5
6
7
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Figure
U65
PCA9548
1 2 C 1-to-8
Bus Switch
IIC_SDA/SCL_MAIN
2
C Bus Topology
2
I C Address
0b1110100
0b1011101
0b1010000
0b0111001
0b1010100
0b0100001
0b1010000
0b0011000
0b1010001
0b1101000
0bxxxxx00
0bxxxxx00
0b1100101
Feature Descriptions
1-22.
CH0 - USRCLK_SFP_SDA/SCL
CH1 - IIC_SDA/SCL_HDMI
CH2 - EEPROM_IIC_SDA/SCL
CH3 - PORT_EXPANDER_SDA/SCL
CH4 - IIC_RTC_SDA/SCL
CH5 - FMC_HPC_IIC_SDA/SCL
CH6 - FMC_LPC_IIC_SDA/SCL
CH7 - PMBUS_DATA/CLK
UG954_c1_22_04113
2
C buses must
2
C address 0x74
Device
PCA9548 U65
Si570 U37
SFP+ Conn. P2
ADV7511 U53
M24C08 U9
Port Expander U16
DDR3 SODIMM J1
RTC8564JE U26
SI5324 U60
FMC HPC J37
FMC LPC J5
UCD90120A U48
[Ref
2
C controller, see Zynq-7000
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26].
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