Ps Power-On And System Reset Pushbuttons - Xilinx ZC706 User Manual

Figure 1-31 shows SW10.
X-Ref Target - Figure 1-31

PS Power-On and System Reset Pushbuttons

Figure 1-32 shows the reset circuitry for the processing system.
X-Ref Target - Figure 1-32
R261 R262 R263
10.0 K 10.0 KΩ 10.0 KΩ
0.1W 0.1W 0.1W
1% 1%
SW2 2
PS_POR_B
1
SW3 2
PS_SRST_B
1
C8 = DNP, SRST delay = 35 µS
C6 = 270 pF, POR delay = 1.08 mS
Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe low.
PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the
required voltage levels. It must be held Low through PS power-up. PS_POR_B should be
generated by the power supply power-good signal.
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
VCC3V3
FPGA_PROG B
Figure 1-31: PROG_B Pushbutton SW10
VCCP1V8 VCCP1V8
R176 R177
8.06 KΩ 8.06 KΩ
0.1W 0.1W
1% 1% 1%
2
3
6
7
13
4
J7
9
8
R256 R264
10.0 Ω
10.0 KΩ
0.1W 0.1W
1% 1%
GND
Figure 1-32: PS Power On and System Reset Circuitry
www.xilinx.com
R73
4.7 kΩ
0.1 W
5%
SW10
2 4
1 3
GND
UG954_c1_31_041113
VCC3V3_PS
U8
MAX16025
Dual Voltage Monitor
R149
and Sequencer
249Ω
1
0.1W
VCC
1%
12
RST_B
IN1
PS_POR_B_SW
11
OUT1
IN2
10 PS_SRST_B_SW
OUT2
EN1
16
CDLY1
EN2
15
CDLY2
MR_B
14
CRESET
TOL
17
EPAD
TH0
5
GND
TH1
0.1 µf
25V
X5R
GND
Feature Descriptions
VCC3V3 VCCP1V8 VCCP1V8
R266
DS1 10.0 KΩ
0.1W
1%
R265
10.0 KΩ
0.1W
1%
PS_POR_B
PS_SRST_B
J44
2
1 3
2
1
3
J43
GND
C6
270pF
25V
C8 X5R
DNP
DNP
xxx
C7
UG954_c1_32_041113
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