Usb 2.0 Ulpi Transceiver - Xilinx ZC706 User Manual

USB 2.0 ULPI Transceiver

[Figure 1-2, callout 19]
The ZC706 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0
ULPI Transceiver at U12 to support a USB connection to the host computer. A USB cable is
supplied in the ZC706 evaluation kit (Standard-A connector to host computer, Micro-B
connector to ZC706 evaluation board connector J2). The USB3320 is a high-speed USB 2.0
PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard
defines the interface between the USB controller IP and the PHY device which drives the
physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB
controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for
clocking mode details
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z045
AP SoC Processor System.
Table 1-7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default OTG mode settings.
Table 1-7: USB Jumper Settings
Header Function
J11 USB PHY reset
J10 V 5V Supply Shunt ON = Host or OTG mode
BUS
J48 RVBUS select
J50 CVBUS select
J49 Cable ID select
USB Micro-B
J51
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
[Ref 17].
Shunt Position
Shunt ON = USB PHY reset
Shunt OFF = USB PHY normal operation
Shunt OFF = Device mode
Position 1–2 = Device mode only (10 KΩ)
Position 2–3 = OTG or Host mode (1 KΩ )
Position 1-2 = OTG and Device mode 1 μ F
Position 2-3 = Host mode 120 μ F
Position 1-2 = A/B cable detect
Position 2-3 = ID not used
Position 1-2 = Shield connected to GND
Position 2-3 = Shield floating
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Feature Descriptions
Notes
Clean reset requires external
debouncing
Overvoltage protection
V load capacitance
BUS
Used in OTG mode
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