Xilinx ZC706 User Manual page 3

Date Version
04/24/2013 1.2
07/31/2013 1.3
04/28/2015 1.4
09/10/2015 1.5
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Chapter 1, ZC706 Evaluation Board
linked to their respective sections in the book.
Figure 1-34 were replaced. Table 1-2 was removed because it was a duplicate of
Table 1-11. Table 1-2: Switch SW11 Configuration Option Settings
Connector JTAG Bypass, page 33
Figure 1-17 was changed.
added. The names of pins 18 and 19 changed in
PMBUS_DATA/CLOCK changed in
to Table 1-27. Callout numbers in the
Table 1-1. SW13 information was added to the section
In Table 1-33, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to
AH27. The section ZC706 Board Power System, page 72
were changed in VADJ Voltage Control, page
Table 1-38 was added.
Appendix A, Default Switch and Jumper
changed.
Appendix G, Regulatory and Compliance
record was added.
Updated Table 1-22. Replaced the master User Constraints File (UCF) list in
Appendix C, Master Constraints File Listing
Constraints (XDC) list. Updated references throughout the document.
Updated "LMZ22000 Family Regulator Description" to
Family Regulator Description. Updated
Table 1-28 through Table
Table A-2. Added Figure A-1. Updated
Updated J48 header jumper setting (third row in
www.xilinx.com
Revision
Features: Table 1-1
Figure
was updated. Default lane size information below
Figure 1-18 PCI Express Lane Size Select Jumper J19
Table
Table 1-25. Reference designator DS35 was added
User I/O, page 57
79. Table 1-37
Settings: The SW11 selection in
Information: A link to the master answer
with the master Xilinx Design
Table 1-4, Table
1-30, Table 1-32 through Table
Appendix C, Master Constraints File
Table
feature descriptions are now
1-2, Figure 1-33, and
was added. FMC
was
2
1-17. The address of I C bus
section are now linked to
User Pushbuttons, page 59.
was added. Voltage levels
was modified and
Table A-1
LMZ31500 and LMZ31700
1-7, Table 1-13, Table 1-23,
1-34, Table 1-36, and
Listing.
1-7).
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