Gth Transceivers - Xilinx DK-V7-VC709-G User Manual

The FPGA EMCC external configuration clock circuit is shown in
X-Ref Target - Figure 1-13
C8
1
0.1UF
10V
2
X5R
GND

GTH Transceivers

[Figure
The VC709 board provides access to 22 GTH transceivers:
•
•
•
The GTH transceivers in 7 series FPGAs are grouped into four channels described as
Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below
the GTH Quad of interest. There are six GTH Quads on the VC709 board with connectivity
as shown here:
•
•
•
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
1
OE
2
GND
U40
Figure 1-13: FPGA External EMCC Clock
1-2, callout 10]
Eight of the GTH transceivers are wired to the PCI Express x8 endpoint edge
connector (P1) fingers.
Ten of the GTH transceivers are wired to the FMC HPC connector (J35).
Four of the GTH transceivers are wired to the four SFP/SFP+ connectors (P2, P3, P4,
P5).
Quad 113:
• MGTREFCLK0 - Si5324 jitter attenuator
• MGTREFCLK1 - SMA clock
• Contains 4 GTH transceivers with one each allocated to SFP 1 through 4
Quad 114:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - No clock
• Contains 4 GTH transceivers for PCIe lanes 4–7
Quad 115:
• MGTREFCLK0 - No clock
www.xilinx.com
VCC1V8
4
VCC
3 FPGA EMCCLK
OUT
SIT8103
SIT8103AC-23-18E-80.0000Y
80.00000MHZ
50PPM
Feature Descriptions
Figure 1-13.
to FPGA U1
pin AP37
UG887_c1_13_052213
35
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