Ddr3 Memory Module - Xilinx AC701 User Manual

Table 1-3: FPGA Bank Voltage Rails (Cont'd)
Bank 34
Bank 35

DDR3 Memory Module

[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM).
It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code
and data. The SODIMM socket has a perforated EMI shield surrounding it as seen in
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The AC701 XC7A200T FPGA memory interface performance is documented in the Artix-7 FPGAs
Data Sheet: DC and AC Switching Characteristics (DS181)
The DDR3 interface is implemented across I/O banks 33, 34, and 35. An external 0.75V reference
VTTREF is provided for these banks. Any interface connected to these banks that requires a
reference voltage must use this FPGA voltage reference. The connections between the DDR3
memory and the FPGA are listed in
Table 1-4: DDR3 Memory Connections to the FPGA
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Power Supply Rail
U1 FPGA Bank
Net Name
FPGA_1V5
FPGA_1V5
1-2, callout 2]
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Configuration: 1GB (128 Mb x 64)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: up to 1,600 MT/s
Schematic Net
FPGA Pin (U1)
Name
M4 DDR3_A0
J3 DDR3_A1
J1 DDR3_A2
L4 DDR3_A3
K5 DDR3_A4
M7 DDR3_A5
K1 DDR3_A6
M6 DDR3_A7
H1 DDR3_A8
K3 DDR3_A9
N7 DDR3_A10
L5 DDR3_A11
L7 DDR3_A12
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Voltage
1.5V
1.5V
[Ref
Table 1-4.
I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
Feature Descriptions
Figure 1-2.
4].
J1 DDR3 Memory
Pin Name
98 A0
97 A1
96 A2
95 A3
92 A4
91 A5
90 A6
86 A7
89 A8
85 A9
107 A10/AP
84 A11
83 A12_BC_N
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