Ddr3 Memory - Xilinx VC707 User Manual
Evaluation board for the virtex-7 fpga
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Also See for VC707:
- User manual (116 pages) ,
- Manual (82 pages) ,
- Getting started (24 pages)
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DDR3 Memory
[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM).
It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code
and data.
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The VC707 XC7VX485T FPGA memory interface performance is documented in the Virtex-7 T
and XT FPGAs Data Sheet: DC and AC Switching Characteristics (DS183)
The DDR3 interface is implemented across I/O banks 37, 38, and 39. Each bank is a 1.5V
high-performance bank having a dedicated DCI VRP/N resistor connection. An external 0.75V
reference VTTREF is provided for data interface banks 37 and 39. Any interface connected to these
banks that requires a reference voltage must use this FPGA voltage reference. The connections
between the DDR3 memory and the FPGA are listed in
Table 1-4: DDR3 Memory Connections to the FPGA
FPGA (U1) Pin
A20
B19
C20
A19
A17
A16
D20
C18
D17
C19
B21
B17
A15
A21
F17
E17
D21
C21
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
1-2, callout 2]
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Supply voltage: 1.5V
Configuration: 1GB (128 Mb x 64)
Datapath width: 64 bits
Data rate: Up to 1,600 MT/s
Net Name
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_A15
DDR3_BA0
DDR3_BA1
www.xilinx.com
Table
I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
Feature Descriptions
[Ref
2].
1-4.
J1 DDR3 Memory
Pin Name
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12_BC_N
119
A13
80
A14
78
A15
109
BA0
108
BA1
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