Encryption Key Backup Circuit - Xilinx ZC702 User Manual

• PL Configuration: USB JTAG configuration port (Digilent module)
• PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
Designs using serial configuration based on Quad-SPI flash memory can take advantage of
TIP:
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in
as described in
configuration details. SW10 is callout
Table 1-2: Switch SW16 Configuration Option Settings
Boot Mode
(1)
JTAG mode
Independent JTAG mode
QSPI mode
SD mode
MIO configuration pin
Notes:
1. Default switch setting
Note: For more information about Zynq-7000 AP SoC configuration settings, see UG585, Zynq-7000
All Programmable SoC Technical Reference Manual.

Encryption Key Backup Circuit

The XC7Z020 AP SoC U1 implements bitstream encryption key technology. The ZC702
board provides the encryption key backup battery circuit shown in
TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the
positive output connected to the XC7Z020 AP SoC U1 VCCBATT pin G9. The battery supply
current IBATT specification is 150 nA maximum when board power is off. B1 is charged from
the VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V
and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Programmable Logic JTAG Programming Options, page 25
SW16.1
0
1
0
0
MIO2
www.xilinx.com
23 in Figure 1-2.
SW16.2 SW16.3
0 0
0 0
0 0
0 1
MIO3 MIO4
Feature Descriptions
Table 1-2 and SW10
for PL
SW16.4 SW16.5
0 0
0 0
1 0
1 0
MIO5 MIO6
Figure 1-5. The Seiko
15