Encryption Key Backup Circuit; Kc705 Board Fpga Configuration Modes; I/O Voltage Rails - Xilinx KC705 User Manual

Table 1-2: KC705 Board FPGA Configuration Modes
Configuration Mode
Master SPI
Master BPI
JTAG
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470) [Ref 2].

Encryption Key Backup Circuit

FPGA U1 implements bitstream encryption key technology. The KC705 board provides the
encryption key backup battery circuit shown in
button-type battery B1 is soldered to the board with the positive output connected to FPGA
U1 VCCBATT pin C10. The battery supply current I
board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series diode with
a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The nominal
charging voltage is 1.62V.
X-Ref Target - Figure 1-4

I/O Voltage Rails

There are 10 I/O banks available on the Kintex-7 device. The voltages applied to the FPGA
I/O banks used by the KC705 board are listed in
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
SW13 DIP Switch
Settings (M[2:0])
001
010
101
D11
40V
200 mW
To FPGA U1 Pin C10
FPGA_VBATT
(VCCBATT)
B1
Figure 1-4: Encryption Key Backup Circuit
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Bus Width
x1, x2, x4
x8, x16
x1
Figure 1-4. The rechargeable 1.5V lithium
specification is 150 nA max when
BATT
NC
1
VCCAUX_IO (2.0V)
3
BAS40-04
2
R406
4.70K 1%
1/16W
1
+
Lithium Battery
Seiko
TS518SE_FL35E
2
GND
UG810_c1_04_031214
Table 1-3.
Send Feedback
CCLK Direction
Output
Output
Not applicable
13