Mitsubishi Electric MELSEC-Q Series User Manual page 382

(b) Master station (RY)  local station (RX), master station (RWw)  local station (RWr)
This is the time between the device of the CPU module in a master station turning on (off) and the device of the
CPU module in a local station turning on (off).
This is also the time between data set in the device of the CPU module in a master station and the data stored
into the device of the CPU module in a local station.
[Formula]
The letters in the table mean as follows.
SM: Master station sequence scan time
LS: Link scan time
SL: Local station sequence scan time
LS SM (The decimal point is rounded up.)
n:
LS × m SM (The decimal point is rounded up.)
t:
LS SL (The decimal point is rounded up.)
k:
m: Constant according to the extended cyclic setting
Expanded Cyclic Setting
With block guarantee of cyclic data per station
Calculation
value
Asynchronous mode
(SM × n) + [LS × {(1 × m) + 1}]
Normal value
+ {SL × (k + 1)}
(SM × n) + [LS × {(2 × m) + 1}]
Max. value
+ {SL × (k + 1)}
When master station sequence scan time is 20ms, link scan time is 3ms, the expanded cyclic setting is
Ex.
"Double", and local station sequence scan time is 10ms
With block guarantee of cyclic data per station
Calculation
value
Asynchronous mode
(20 × 1) + [3 × {(1 × 3) + 1}] +
Normal value {10 × (1 + 1)}
= 52ms
(20 × 1) + [3 × {(2 × 3) + 1}] +
Max. value {10 × (1 + 1)}
= 61ms
(6) Master station ↔ intelligent device station
Transmission delay time between a master station and an intelligent device station varies depending on the
intelligent device station.
Refer to the user's manual for the intelligent device module used.
380
Single
m
Synchronous mode
{(SM × t) × 1} + {SL ×
(k + 1)}
{(SM × t) × 2} + {SL×
(k + 1)}
Synchronous mode
{(20 × 1) × 1} + {10 ×
(1 + 1)} = 40ms
{(20 × 1) × 2} + {10 ×
(1 + 1)} = 60ms
Double
1 3
Without block guarantee of cyclic data per station
Asynchronous mode
SM + [LS × {(1 × m) + 1}] +
SL
SM + [LS × {(2 × m) + 1}] +
SL
Without block guarantee of cyclic data per station
Asynchronous mode
20 + [3 × {(1 × 3) + 1}] + 10 =
42ms
20 + [3 × {(2 × 3) + 1}] + 10 =
51ms
Quadruple Octuple
7 15
Synchronous mode
{(SM × t) × 1} + SL
{(SM × t) × 2} + SL
Synchronous mode
{(20 × 1) × 1} + 10
= 30ms
{(20 × 1) × 2} + 10
= 50ms