Direct Rambus* Clock Routing; Direct Rambus* Design Checklist; Signal List - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
2.6.5 Direct Rambus
Refer to Chapter 4, "Clocking"
guidelines.
2.6.6

Direct Rambus* Design Checklist

Use the following checklist as a final check to ensure the motherboard incorporates solid design
practices. This list is only a reference. For correct operation, all of the design guidelines within this
document must be followed.
Table 2-6. Signal List
RSL Signals
DQA[8:0]
DQB[8:0]
RQ[7:0]
•
Ground Isolation Well Grounded
— Via to ground every ½ inch around edge of isolation island
— Via to ground every ½ inch between RIMMs
— Via to ground every ½ inch between signals (from MCH to first RIMM)
— Via between every signal within 100mils of the MCH edge and the connector edge
— No unconnected ground floods
— All ground isolation at least 10 mils wide
— Ground isolation fills between serpentines
— Ground isolation not broken by C-TABs
— Ground isolation connects to the ground pins in the middle of the RIMM connectors
— Ground isolation vias connect on all 4 layers and should NOT have thermal reliefs
— Ground pins in RIMM connector connect on all 4 layers
•
Vterm Layout Yields Low Noise
— Solid Vterm island is on top layer – do not split this plane
— Ground island (for ground side of Vterm caps) is on top
— Termination Resistors connect DIRECTLY to the Vterm island on the top layer (without
vias)
— Decoupling Vterm is CRITICAL!
— Decoupling capacitors connect to top layer Vterm island and top layer ground island
directly (see layout example)
— Use AT LEAST 2 vias per decoupling capacitor in the top layer ground island
— Use 2 x 100 uF TANTALUM capacitors to decouple Vterm
(Aluminum/Electrolytic capacitors are too slow!)
— High-frequency decoupling capacitors MUST be spread-out across the termination island
so that all termination resistors are near high-frequency capacitors
— 100uF TANTALUM capacitors should be at each end of the Vterm island
— 100uF TANTALUM capacitors must be connected to Vterm island directly
— 100uF TANTALUM capacitors must have AT LEAST 2 vias/cap to ground
2-28
*
Clock Routing
®
for Intel 820 chipset platform Direct Rambus
High-Speed
Serial CMOS Signal
CMOS Signals
CMD
SCK
*
clock routing
Clocks
CTM
CTM#
SIO
CFM
CFM#
®
Intel 820 Chipset Design Guide