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TOOLS
16.2.5. Debug Port Layout
Figure 16-4 shows the simplest way to layout the debug port in a multiprocessor system. In this
example, the four processors are the only components in the system boundary scan chain. Sys-
tems incorporating boundary scan for use other than for an ITP should consider providing a
method to partition the boundary scan chain in two distinct sections; one for system debug using
the ITP and the other for manufacturing or system test.
System debug using an ITP requires only that the Pentium Pro processors be in the boundary
scan chain. During system debug, routing boundary scan signals (particularly TCK and TMS)
solely to the Pentium Pro processors enhances the likelihood that the boundary scan signals can
be clocked at high speed. This will improve the performance of debug tools that must access
large amounts of data via boundary scan. (For example, MP systems that have up to four proces-
sor in the chain will require four times as much boundary scan traffic.) Additionally, removing
all but the Pentium Pro processors from the boundary scan chain reduces the possibility for er-
rors in the chain when using an ITP for system debug.
If your system includes the use of boundary scan for test during normal system operation, then
you should consider including the QST3383 in your layout. This component is used to multiplex
the boundary scan lines in order to avoid contention between the system and an ITP. Using the
QST3383, the system boundary scan lines are routed directly to the system when an ITP is not
installed.
However, if the ITP is installed and is communicating with the Pentium Pro processors, the BS-
EN# signal will enable the multiplexer to pass the boundary scan lines from the debug port to
the system. Note: When an ITP is installed and communicating with the processors, the TDI line
from the system boundary scan control logic does not pass through to the system, but is instead
tied back into the TDO line. Thus, while the ITP is communicating with the processors, it is not
possible for the system boundary scan control logic to access a processor via the boundary scan
chain.
16-7
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