Figure 11-4. Example Schematic For Clock Ratio Pin Sharing - Intel Pentium Pro Family Developer's Manual

ELECTRICAL SPECIFICATIONS
Using CRESET# (CMOS reset), the circuit in Figure 11-4 can be used to share the pins. The pins
of the processors are bussed together to allow any one of them to be the compatibility processor.
The component used as the multiplexer must not be powered by more than 3.3V in order to meet
the Pentium Pro processor's 3.3V tolerant buffer specifications. The multiplexer output current
should be limited to 200mA max, in case the V cc P supply ever fails to the processor.
The pull-down resistors between the multiplexer and the processor (1KΩ) force a ratio of 2x into
the processor in the event that the Pentium Pro processor powers up before the multiplexer
and/or the chipset. This prevents the processor from ever seeing a ratio higher than the final
ratio.
A20M#
IGNNE#
LINT1/NMI
LINT0/INTR
Set Ratio:
CRESET#

Figure 11-4. Example Schematic for Clock Ratio Pin Sharing

If the multiplexer were powered by V cc P, CRESET# would still be unknown until the 3.3V sup-
ply came up to power the CRESET# driver. A pull-down can be used on CRESET# instead of
the four between the multiplexer and the Pentium Pro processor in this case. In this case, the
multiplexer must be designed such that the compatibility inputs are truly ignored as their state
is unknown.
In any case, the compatibility inputs to the multiplexer must meet the input specifications of the
multiplexer. This may require a level translation before the multiplexer inputs unless the inputs
and the signals driving them are already compatible.
For FRC mode processors, one multiplexer will be needed per FRC pair, and the multiplexer will
need to be clocked using BCLK to meet setup and hold times to the processors. This may require
the use of high speed programmable logic.
11-6
3.3V
1K Ω
3.3V
Mux
1K Ω
P6
P6
®
Pentium
P6
Pro
Processor