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BUS TRANSACTIONS AND OPERATIONS
This chapter describes in detail the bus transactions and operations supported by the Pentium
Pro processor bus.
5.1.
BUS TRANSACTIONS SUPPORTED
Figure 5-1 lists the different bus transactions.
Memory
Read data:
Mem Read
Mem (Read) Invalidate LIne
Write data:
Mem Write
Deferred:
No Data:
The transactions classified as read data transactions normally expect a response initiated data
transfer from the agent addressed by the transaction. This is indicated by a Normal Data
Response in the Response Phase of the transaction. If no bytes are enabled, then a No Data Re-
sponse is returned by the addressed agent.
The transactions classified as write data transactions require request-initiated data transfer and
are identified by REQa[0]#. All responses except Normal Data Response are allowed. The target
asserts TRDY#. Implicit Writeback Responses may also occur and send additional snoop initi-
ated data.
All Bus Transactions
I/O
I/O Read
I/O Write
Figure 5-1. Bus Transactions
CHAPTER 5
Other
Interrupt Acknowledge
Branch Trace Message
Deferred Reply
Shutdown
Flush
Halt
Sync
Flush Acknowledge
Stop Grant Acknowledge
SMI Acknowledge
5-1
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