Table A-10. Transaction Response Encodings; A.1.45. Rs[2:0]#(I) - Intel Pentium Pro Family Developer's Manual

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SIGNALS REFERENCE
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered sig-
nals are high.

A.1.45. RS[2:0]#(I)

The RS[2:0]# signals are the Response Status signals. They are driven by the response agent (the
agent responsible for completion of the transaction at the top of the In-order Queue). Assertion
of RS[2:0]# to a non-zero value for one clock completes the Response Phase for a transaction.
The response encodings are shown in Table A-10. Only certain response combinations are valid,
based on the snoop result signaled during the transaction's Snoop Phase.

Table A-10. Transaction Response Encodings

RS[2:0]#
000
Idle State.
001
Retry Response. The transaction is cancelled and must be
retried by the initiator.
010
Defer Response. The transaction is suspended. The defer agent
will complete it with a defer reply
011
Reserved.
100
Hard Failure. The transaction received a hard error. Exception
handling is required.
101
Normal without data
110
Implicit Writeback Response. Snooping agent will transfer the
modified cache line on the data bus.
111
Normal with data.
The RS[2:0]# assertion for a transaction is initiated when all of the following conditions are met:
All bus agents have observed the Snoop Phase completion of the transaction.
The transaction is at the top of the In-order Queue.
RS[2:0]# are sampled in the Idle state
The response driven depends on the transaction as described below:
The response agent returns a hard-failure response for any transaction in which the
response agent observes a hard error.
The response agent returns a Normal with data response for a read transaction with HITM#
and DEFER# deasserted in the Snoop Phase, when the addressed agent is ready to return
data and samples inactive DBSY#.
A-20
Description
HITM#
DEFER#
NA
NA
0
1
0
1
0
1
X
X
0
0
1
X
0
0

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