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SIGNALS REFERENCE
The deferred identifier defines the token supplied by the request initiator. DID[7:4]# carry the
request initiators' agent identifier and DID[3:0]# carry a transaction identifier associated with
the request. This configuration limits the bus specification to 16 bus masters with each one of
the bus masters capable of making up to sixteen requests.
Every deferrable transaction issued on the Pentium Pro processor bus which has not been guar-
anteed completion (has not successfully passed its Snoop Result Phase) will have a unique De-
ferred ID. This includes all outstanding transactions which have not had their snoop result
reported, or have had their snoop results deferred. After a deferrable transaction passes its Snoop
Result Phase without DEFER# asserted, its Deferred ID may be reused. Similarly, the deferred
ID of a transaction which was deferred may be reused after the completion of the snoop window
of the deferred reply.
DID[7]# indicates the agent type. Symmetric agents use 0. Priority agents use 1. DID[6:4]# in-
dicates the agent ID. Symmetric agents use their arbitration ID. The Pentium Pro processor has
four symmetric agents, so does not assert DID[6]#. DID[3:0]# indicates the transaction ID for
an agent. The transaction ID must be unique for all transactions issued by an agent which have
not reported their snoop results.
Table A-6. DID[7:0]# Encoding
DID[7]#
DID[6:4]#
DID[3:0]#
Agent Type
Agent ID
Transaction ID
The Deferred Reply agent transmits the DID[7:0]# (Ab[23:16]#) signals received during the
original transaction on the Aa[23:16]# signals during the Deferred Reply transaction. This pro-
cess enables the original request initiator to make an identifier match and wake up the original
request waiting for completion.
A.1.24. DRDY# (I/O)
The DRDY# signal is the Data Phase data-ready signal. The data driver asserts DRDY# on each
data transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be
deasserted to insert idle clocks in the Data Phase. During a line transfer, DRDY# is active for
four clocks. During a partial 1-to-8 byte transfer, DRDY# is active for one clock. If a data trans-
fer is exactly one clock, then the entire Data Phase may consist of only one clock active DRDY#
and inactive DBSY#. If DBSY# is asserted for a 1-to-8 byte transfer, then the data bus is not
released until one clock after DBSY# is deasserted.
A.1.25. DSZ[1:0]# (I/O)
The DSZ[1:0]# signals are the data-size signals. They are transferred on REQb[4:3]# signals in
the second clock of Request Phase by the requesting agent. The DSZ[1:0]# signals define the
data transfer capability of the requesting agent. For the Pentium Pro processor, DSZ#= 00,
always.
A-12
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