Full Speed Write Line Transactions (Same Agents); Figure 4-24. Full Speed Write Partial Transactions - Intel Pentium Pro Family Developer's Manual

BUS PROTOCOL
1 2
CLK
1
ADS#
A A AAA AA
1
{REQUEST}
HIT#
TRDY#
DBSY#
A AAAAAA A A AAAAAA
D[63:0]#
DRDY#
RS[2:0]#

Figure 4-24. Full Speed Write Partial Transactions

In the example, the data transfer only takes one clock, so DBSY# is not asserted.
Write Partial Transactions are driven at full speed. The first transaction occurs on an idle bus and
looks just like the simple write case in Figure 4-18. TRDY# is driven 3 clocks later in T4. The
Normal No Data response is driven in T7 after inactive HITM# sampled in T6 indicates no im-
plicit writeback. TRDY# is observed active and DBSY# is observed inactive in T5. Therefore
the data transfer can begin in T6 as indicated by DRDY# assertion.
The TRDY# for transaction 2 must wait until the response for transaction 1 is sampled. TRDY#
is asserted the cycle after RS[2:0]# is sampled. Because the snoop results for transaction 2 have
been observed in T9, the response may be driven on RS[2:0]# in T10. TRDY# is sampled with
DBSY# deasserted in T10 and data is driven in T11.
There are no bottlenecks to maintaining this steady state.
4.6.2.8.

FULL SPEED WRITE LINE TRANSACTIONS (SAME AGENTS)

Figure 4-25 shows the steady-state behavior of the bus with full speed Write Line Transactions
with data transfers from the same request agent to the same addressed agent.Data transfers may
occur without a turn-around cycle only if from the same agent.
4-40
3 4 5 6 7
2 3
AAA A A A A AAA A A A AAA A A AAA A
2 3
1
1
AA AAAAAA A AA AA AAAAAA A A AAAAAA A A AA A A AAA A A AAAAAA A A
1
1
8 9 10 11 12 13
4 5
A A AAA A A AAA A A AA AAA A A AAA A
4 5
2 3
2 3
A AAAAAA AA AAAAAA AA A A AAA A AA A AA AAAA AAAAAA AA
2
2 3
14 15 16
6
AAAA A A AA A A AAA
6
4
4
A A A AAA AA A AA AAAA AA AAAAAA AA
3
4