Sync; Flush Acknowledge; Stop Grant Acknowledge; Smi Acknowledge - Intel Pentium Pro Family Developer's Manual

.
Event
INTR
NMI
INIT#
RESET#
STPCLK#
SMI#
FLUSH#
ADS#
BINIT#
HardFail
FRCERR
5.2.3.6.4.

Sync

An agent issues a Sync Transaction to indicate that it has written back all modified lines in its
internal caches to memory and then invalidated its internal caches. If software wants to guaran-
tee that other processors are also synchronized, it must do so via APIC IPIs. The Pentium Pro
processor generates a Sync Transaction on executing a WBINVD instruction.
5.2.3.6.5.

Flush Acknowledge

A caching agent issues a Flush Acknowledge Transaction when it has completed a cache sync,
and flush operation in response to an earlier FLUSH# signal activation. If FLUSH# pin is bussed
to N agents, the Central Agent must expect N Flush Acknowledge transactions.
5.2.3.6.6.

Stop Grant Acknowledge

An agent issues a Stop Grant Acknowledge Transaction when it enters Stop Grant mode.
The agent continues to respond to RESET#, BINIT#, ADS#, and FLUSH# while in Stop Grant
mode. The Pentium Pro processor powers down its caches in the Stop Grant mode to minimize
its power consumption and generates a delayed snoop response on an external bus snoop
request.
5.2.3.6.7.

SMI Acknowledge

An agent issues an SMI Acknowledge Transaction when it enters the System Management
Mode handler. SMMEM# (Ab[7]#) is first asserted at this entry point. It remains asserted for all
transactions issued by the agent. An agent issues another SMI Acknowledge Transaction when
it exits the System Management Mode handler. SMMEM# (Ab[7]#) is first deasserted at this exit
point.
Immediate Action
Interrupt Handler Entry
NMI Handler Entry
Reset Handler
Reset Handler
STPCLK Acknowledge
SMI Handler Entry
FLUSH Acknowledge
Snoop Results
MCA Handler Entry
MCA Handler Entry
MCA Handler Entry
BUS TRANSACTIONS AND OPERATIONS
Final State
Do not return to Halt on IRET
Do not return to Halt on IRET
Do not return to Halt
Do not return to Halt
Return to Halt on !STPCLK
Optionally return to Halt on RSM based on a
bit setting in SMRAM
Return to Halt Immediately
Return to halt Immediately
Do not return to Halt
Do not return to Halt
Do not return to Halt
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