11.15. A.c. Specifications; Table 11-9. Bus Clock A.c. Specifications - Intel Pentium Pro Family Developer's Manual

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ELECTRICAL SPECIFICATIONS

11.15. A.C. SPECIFICATIONS

Table 11-9 through Table 11-16 list the A.C. specifications associated with the Pentium Pro pro-
cessor. Timing Diagrams begin with Figure 11-7. The AC specifications are broken into catego-
ries. Table 11-9 and Table 11-10 contain the clock specifications, Table 11-11 and Table 11-12
contain the GTL+ specifications, Table 11-13 contains the 3.3V tolerant Signal group specifica-
tions, Table 11-14 contains timings for the reset conditions, Table 11-15 covers APIC bus tim-
ing, and Table 11-16 covers Boundary Scan timing.
All A.C. specifications for the GTL+ signal group are relative to the rising edge of the BCLK
input. All GTL+ timings are referenced to V REF for both "0" and "1" logic levels unless other-
wise specified.
Care should be taken to read all notes associated with a particular timing parameter.
T#
Parameter
Core Frequency
Bus Frequency
T1:
BCLK Period
T2:
BCLK Period Stability
T3:
BCLK High Time
T4:
BCLK Low Time
T5:
BCLK Rise Time
T6:
BCLK Fall Time
NOTES:
1. The internal core clock frequency is derived from the bus clock. A clock ratio must be driven into the Pen-
tium
®
Pro processor on the signals LINT[1:0], A20M# and IGNNE# at reset. See the descriptions for
these signals in Appendix A. See Table 11-10 for a list of tested ratios per product.
2. Not 100% tested. Guaranteed by design/characterization.
3. Measured on rising edge of adjacent BCLKs at 1.5V.
The jitter present must be accounted for as a component of BCLK skew between devices.
Clock jitter is measured from one rising edge of the clock signal to the next rising edge at 1.5V. To remain
within the clock jitter specifications, all clock periods must be within 300ps of the ideal clock period for a
given frequency. For example, a 66.67 MHz clock with a nominal period of 15ns, must not have any sin-
gle clock period that is greater than 15.3ns or less than 14.7ns.
11-18

Table 11-9. Bus Clock A.C. Specifications

Min
Max
100
150
150
166.67
150
180
150
200
50.00
66.67
15
20
300
4
4
0.3
1.5
0.3
1.5
Unit
Figure
Notes
MHz
@ 150MHz
MHz
@ 166MHz
MHz
@ 180MHz
MHz
@ 200MHz
1
All Frequencies 1
MHz
ns
11-7
All Frequencies
2 , 3
ps
@>2.0V, 2
ns
11-7
@<0.8V, 2
ns
11-7
(0.8V - 2.0V), 2
ns
11-7
(2.0V- 0.8V), 2
ns
11-7

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