Implicit Writeback; Figure 4-19. Response Initiated Data Transfer - Intel Pentium Pro Family Developer's Manual

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CLK
ADS#
REQa0#
HITM#
TRDY#
DBSY#
D[63:0]#
DRDY#
RS[2:0]#

Figure 4-19. Response Initiated Data Transfer

A read transaction is driven in T1 as indicated by the ADS# and REQa0# pins. Because the trans-
action is a read and HITM# indicates that there will be no implicit writeback data, TRDY# is not
asserted for this transaction.
The response for this transaction is driven on RS[2:0]# in T7, two clocks after the snoop results
are driven in T5. For read transactions (response initiated data transfers), the data transfer must
begin in the same clock that the response is driven.
4.6.2.3.

IMPLICIT WRITEBACK

Figure 4-20 shows a simple implicit writeback (snoop-initiated data transfer) occurring during
a read transfer transaction. Note that wait states can be added into the data transfer by the deas-
sertion of DRDY#. Note also that the data transfer for the implicit writeback must begin on the
same clock that the response is driven on RS[2:0]#.
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