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12.2.3.2.
MINIMUM SETUP AND HOLD TIMES
Setup time for GTL+ (T
SU
The minimum time from the input signal pin crossing of V
pin of the receiver crossing the 1.5 V level, which guarantees that the input
buffer has captured new data at the input pin, given an infinite hold time.
Strictly speaking, setup time must be determined when the input barely meets minimum hold
time (see definition of hold time below). However, for current GTL+ systems, hold time should
be met well beyond the minimum required in cases where setup is critical. This is because setup
is critical when the receiver is far removed from the driver. In such cases, the signal will be held
at the receiver for a long time after the clock, since the change needs a long time to propagate
from the driver to the receiver.
The recommended procedure for the I/O buffer designer to extract T
employs additional steps, it would be beneficial that any such extra steps be documented with
the results of this receiver characterization:
The full receiver circuit must be used, comprising the input differential amplifier, any
•
shaping logic gates, and the edge-triggered (or pulse-triggered) flip-flop. The output of the
flip-flop must be monitored.
The receiver's Lo-to-Hi setup time should be determined using a nominal input waveform
•
like the one shown in Figure 12-13 (solid line). The Lo-to-Hi input starts at V
(V
- 200 mV) and goes to V
REF
0.3V/ns, with the process, temperature, voltage, and V
the worst (longest T
voltage at the device pin. Due to tolerance in V
generating system V
±122 mV. When determining setup time, the internal reference voltage V
the reference gate of the diff. amp.) must be set to the value which yields the longest setup
time. Here, V
REF_INTERNAL
maximum differential noise amplitude on the component's internal V
(at the amplifier's reference input gate) comprising noise picked up by the connection from
the V
package pin to the input of the amp.
REF
Analogously, for the setup time of Hi-to-Lo transitions (Figure 12-14), the input starts at
•
V
= V
IN_HIGH_MIN
REF
of 0.3V/ns.
For both the 0.3V/ns edge rate and faster edge rates (up to 0.8V/ns for Lo-to-Hi, and 3V/ns
•
for Hi-to-Lo —dashed lines in Figure 12-13 and Figure 12-14), one must ensure that lower
starting voltages of the input swing (V
to-Hi transitions, and 1.5 V to 'V
Figure 12-13 and Figure 12-14) do not require T
since a lower starting voltage may cause the input differential amplifier to require more
time to switch, due to having been in deeper saturation in the initial state.
) is defined as:
IN_HIGH_MIN
) corner values. Here, V
SU
from V
(±2%), V
REF
TT
= V
±(122 mV +V
REF
+200 mV and drops to V
START
+200 mV' for Hi-to-Lo transitions —dashed lines in
REF
GTL+ INTERFACE SPECIFICATION
to the clock
REF
is outlined below. If one
SU
= V
+200 mV, at a slow edge rate of
REF
REF_INTERNAL
is the external (system) reference
REF
(1.5V, ±10%) and the voltage divider
TT
can shift around 1 V by a maximum of
REF
). Where, V
NOISE
= V
IN_LOW_MAX
REF
in the range 'V
-200 mV' to 0.5 V for Lo-
REF
to be made longer. This step is needed
SU
IN_LOW_MAX
of the receiver set to
(at
REF_INTERNAL
is the net
NOISE
distribution bus
REF
- 200 mV at the rate
12-19
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