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SIGNALS REFERENCE
Table A-13. Input/Output Signals (Single Driver)(Contd.)
Name
Active Level
D[63:0]#
Low
DBSY#
Low
DEN#
Low
DEP[7:0]#
Low
DID[7:0]#
Low
DSZ[1:0]#
Low
DRDY#
Low
EXF[4:0]#
Low
FRCERR
High
LEN[1:0]#
Low
LOCK#
Low
REQ[4:0]#
Low
RP#
Low
SMMEM#
Low
SPLCK#
Low
A-26
Clock
Signal Group
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Implementation
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
BCLK
Pentium Pro
processor bus
Qualified
DRDY#
Always
ADS# + 1
DRDY#
ADS#+1
ADS#+1
Always
ADS#+1
Always
ADS#+1
Always
ADS#, ADS#+1
Always
ADS# + 1
ADS# + 1
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