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SIGNALS REFERENCE
A.1.12. BNR# (I/O)
The BNR# signal is the Block Next Request signal in the Arbitration group. The BNR# signal
is used to assert a bus stall by any bus agent who is unable to accept new bus transactions to avoid
an internal transaction queue overflow. During a bus stall, the current bus owner cannot issue
any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR
signal. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven
by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock
edges. A valid bus stall involves assertion of BNR# for one clock on a well-defined clock edge
(T1), followed by de-assertion of BNR# for one clock on the next clock edge (T1+1). BNR# can
first be sampled on the second clock edge (T1+1) and must always be ignored on the third clock
edge (T1+2). An extension of a bus stall requires one clock active (T1+2), one clock inactive
(T1+3) BNR# sequence with BNR# sampling points every two clocks (T1+1, T1+3,...).
After the RESET# active-to-inactive transition, bus agents might need to perform hardware ini-
tialization of their bus unit logic. Bus agents intending to create a request stall must assert BNR#
in the clock after RESET# is sampled inactive.
After BINIT# assertion, all bus agents go through a similar hardware initialization and can cre-
ate a request stall by asserting BNR# four clocks after BINIT# assertion is sampled.
On the first BNR# sampling clock that BNR# is sampled inactive, the current bus owner is al-
lowed to issue one new request. Any bus agent can immediately reassert BNR# (four clocks
from the previous assertion or two clocks from the previous de-assertion) to create a new bus
stall. This throttling mechanism enables independent control on every new request generation.
If BNR# is deasserted on two consecutive sampling points, new requests can be freely generated
on the bus. After receiving a new transaction, a bus agent can require an address stall due to an
anticipated transaction-queue overflow condition. In response, the bus agent can assert BNR#,
three clocks from active ADS# assertion and create a bus stall. Once a bus stall is created, the
bus remains stalled until BNR# is sampled asserted on subsequent sampling points.
A.1.13. BP[3:2]# (I/O)
The BP[3:2]# signals are the System Support group Breakpoint signals. They are outputs from
the Pentium Pro processor that indicate the status of breakpoints.
A.1.14. BPM[1:0]# (I/O)
The BPM[1:0]# signals are more System Support group breakpoint and performance monitor
signals. They are outputs from the Pentium Pro processor that indicate the status of breakpoints
and programmable counters used for monitoring Pentium Pro processor performance.
A-7
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