Bus Signals - Intel Pentium Pro Family Developer's Manual

BUS PROTOCOL
Besides the two classes of arbitration agents, each bus agent has two actions available that act
as arbitration modifiers: the bus lock and the request stall.
The bus lock action is available to the current symmetric owner to block other agents, including
the priority agent from acquiring the bus. Typically a bus locked operation consists of two or
more transactions issued on the bus as an indivisible sequence (this is indicated on the bus by
the assertion of the LOCK# pin). Once the symmetric bus owner has successfully initiated the
first bus locked transaction it continues to issue remaining requests that are part of the same in-
divisible operation without releasing the bus.
The request stall action is available to any bus agent that is unable to accept new bus transactions.
By asserting a signal (BNR#) any agent can prevent the current bus owner from issuing new
transactions.
In summary, the priority for entering the Request Transfer Phase, assuming there is no bus stall
or arbitration reset event, is:
1. The current bus owner retains ownership until it completes an ongoing indivisible bus
locked operation.
2. The priority agent gains bus ownership over a symmetric owner.
3. Otherwise, the current symmetric owner as determined by the rotating priority is allowed
to generate new transactions.
4.1.2.

Bus Signals

The Arbitration Phase signals are BREQ[3:0]#, BPRI#, BNR#, and LOCK#.
BREQ[3:0]# bus signals are connected to the four symmetric agents in a rotating manner as
shown in Figure 4-1. This arrangement initializes every symmetric agent with a unique Agent
ID during power-on configuration. Every symmetric agent has one input/output pin, BR0#, to
arbitrate for the bus during normal operation. The remaining three pins, BR1#, BR2#, and BR3#,
are input only and are used to observe the arbitration requests of the remaining three symmetric
agents.
At reset, the central agent is responsible for asserting the BREQ0# bus signal. BREQ[3:1]#
remain deasserted. All Pentium Pro processors sample BR[3:1]# on the active to inactive tran-
sition of RESET# to determine their arbitration IDas follows :
The BR1#, BR2#, and BR3# pins are all inactive on Agent 0.
•
Agent 1 has BR3# active.
•
Agent 2 has BR2# active.
•
Agent 3 has BR1# active.
•
The BPRI# signal is an output from the priority agent by which it arbitrates for the bus owner-
ship and an input to the symmetric agents. The LOCK# and BNR# signals are bi-directional sig-
nals bused among all agents. The current bus owner uses LOCK# to define an indivisible bus
locked operation. BNR# is used by any bus agent to stall further request phase initiation.
4-2