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GTL+ INTERFACE SPECIFICATION
Symbol
Parameter
dV/dt
Output Signal Edge Rate, rise
EDGE
dV/dt
Output Signal Edge Rate, fall
EDGE
T
Output Clock to Data Time
CO
T
Input Setup Time
SU
T
Input Hold Time
HOLD
NOTES:
1. This is the maximum instantaneous dV/dt over the entire transition range (Hi-to-Lo or Lo-to-Hi) as mea-
sured at the driver's output pin while driving the Ref8N network, with the driver and its package model
located near the center of the network (see Section 12.4., "Ref8N Network").
2. These are design targets. The acceptance of the buffer is also based on the resultant signal quality. In
addition to edge rate, the shape of the rising edge can also have a significant effect on the buffer's perfor-
mance, therefore the driver must also meet the signal quality criteria in the next section. For example, a
rising linear ramp of at 0.8V/ns will generally produce worse signal quality (more ringback) than an edge
that rolls off as it approaches V
rates may exceed this specification and produce acceptable results with a corresponding reduction in
V
. For instance, a buffer with a falling edge rate larger than 1.5V/ns can been deemed acceptable
OL
because it produced a V
OL
edge rate specifications.
3. The minimum edge rate is a design target, and slower edge rates can be acceptable, although there is a
timing impact associated with them in the form of an increase in flight time, since the signal at the receiver
will no longer meet the required conditions for T
Time" on computing flight time for more details on the effects of edge rates slower than 0.3V/ns.
4. These values are not specific to this specification, they are dependent on the location of the driver along
a network and the system requirements such as the number of agents, the distances between agents,
the construction of the PCB (Z
and the value of the termination resistors. Good targets for components to be used in an 8-load 66.6 MHz
system would be: T
CO_MAX
5. This value is specified at the output pin of the device. T
shown in the Figure 12-11, but the delay caused by the 50Ω transmission line must be subtracted from
the measurement to achieve an accurate value for Tco at the output pin of the device. For simulation pur-
poses, the tester load can be represented as a single 25Ω termination resistor connected directly to the
pin of the device.
6. See Section 12.2.3., "Determining Clock-To-Out, Setup and Hold" for a description of the procedure for
determining the receiver's minimum required setup and hold times.
12-14
Table 12-5. I/O Buffer AC Parameters
Min
0.3
0.3
even though it might have exceeded that rate earlier. Hi-to-Lo edge
TT
less than 500 mV. Lo-to-Hi edges must meet both signal quality and maximum
. Refer to Section 12.1.4., "AC Parameters: Flight
SU
, εr, trace width, trace type, connectors), the sockets being used, if any,
0
= 4.5 ns, T
= 1 ns, T
CO_MIN
Max
Units
0.8
V/ns
-0.8
V/ns
no spec
ns
Figure 12-12
no spec
ns
Figure 12-13
Figure 12-14
no spec
ns
= 2.5 ns, and T
= 0.
SU
HD
should be measured at the test probe point
CO
Figure
Notes
1, 2, 3
1, 2, 3
4, 5
4, 6
4, 6
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