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GTL+ INTERFACE SPECIFICATION
12.1.2. Topological Guidelines
The board routing should use layout design rules consistent with high-speed digital design (i.e.
minimize trace length and number of vias, minimize trace-to-trace coupling, maintain consistent
impedance over the length of a net, maintain consistent impedance from one net to another, en-
sure sufficient power to ground plane bypassing, etc.). In addition, the signal routing should be
done in a Daisy Chain topology (such as shown in Figure 12-1) without any significant stubs.
Table 12-2 describes, more completely, some of these guidelines. Note that the critical distances
are measured in electrical length (propagation time) instead of physical length.
Symbol
Maximum Trace Length
To meet a specific Clock cycle time, the maximum trace length between any two
agents must be restricted. The flight time (defined later) must be less than or
equal to the maximum amount of time which leaves enough time within one
clock cycle for the remaining system parameters such as driver clock-out delay
(T
Maximum Stub Length
All signals should use a Daisy Chain routing (i.e. no stubs). It is acknowledged
that the package of each device on the net imposes a stub, and that a practical
layout using PQFP parts may require SHORT stubs, so a truly stubless network
is impossible to achieve, but any stub on the network (including the device
package) should be no greater than 250 ps in electrical length.
Distributed Loads
Minimum spacing lengths are determined by hold time requirements and clock
skew. Maintaining 3" ±30% inter-agent spacing minimizes the variation in noise
margins between the various networks, and can provide a significant
improvement for the networks. This is only a guideline.
12.1.3. System AC Parameters: Signal Quality
The system AC parameters fall into two categories, Signal Quality and Flight Time. Acceptable
signal quality must be maintained over all operating conditions to ensure reliable operation. Sig-
nal Quality is defined by three parameters: Overshoot/ Undershoot, Settling Limit, and Ring-
back. These parameters are illustrated in Figure 12-2 and are described in Table 12-3.
12-4
Table 12-2. System Topological Guidelines
), receiver setup time (T
CO
Parameter
), clock jitter and clock skew.
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