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CACHE PROTOCOL
— E (Exclusive)
The line is in this cache, contains the same value as in memory, and is Invalid in all
other caches. Internally reading the line causes no bus activity. Internally writing the
line causes no bus activity, but changes the line's state to Modified.
— M (Modified)
The line is in this cache, contains a more recent value than memory, and is Invalid in
all other caches. Internally reading or writing the line causes no bus activity.
A line is valid in a cache if it is in the Shared, Exclusive, or Modified state.
7.2.
MEMORY TYPES, AND TRANSACTIONS
A number of bus and processor transactions can cause a line to transition from one state to an-
other. The transaction being executed, a line's present state, snoop results, and memory range
attributes combine to determine a line's new state and coherency-related bus activity (such as
writebacks). This section describes the snoop result signals, memory types, and transaction
types, the overall state transition diagram, and the possible final states for different bus
transactions.
7.2.1.
Memory Types: WB, WT, WP, and UC
Each line has a memory type determined by the Pentium Pro processor's range registers and con-
trol registers, described in Chapter 6, Range Registers. For caching purposes, the memory type
can be writeback (WB), write-through (WT), write-protected (WP), or un-cacheable (UC).
A WB line is cacheable and is always fetched into the cache if a miss occurs. A write to a WB
line does not cause bus activity if the line is in the E or M states.
A WT line is cacheable but is not fetched into the cache on a write miss. A write to a WT line
goes out on the bus. For the Pentium Pro processor, a WT hit to the L1 cache updates the L1
cache. A WT hit to L2 cache invalidates the L2 cache.
A WP line is also cacheable, but a write to it cannot modify the cache line and the write always
goes out on the bus. A WP line is not fetched into the cache on a write miss. For the Pentium
Pro processor, a WP hit to the L2 cache invalidates the line in the L2 cache.
An UC line is not put into the cache. A UC hit to the L1 or L2 cache invalidates the entry.
7.2.2.
Bus Operations
In this chapter, the bus transactions described in Chapter 5, Bus Transactions and Operations are
classified into the following generic groups for ease of presentation:
BRL (Bus Read Line). A Bus Read Line transaction is a Memory Read Transaction for a full
cache line. This transaction indicates that a requesting agent has had a read miss.
7-2
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