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The following is a brief description of each of the states of the TAP controller state machine.
Refer to the IEEE 1149.1 standard for detailed descriptions of the states and their operation.
Test-Logic-Reset: In this state, the test logic is disabled so that normal operation of the
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Pentium Pro processor can continue. In this state, the instruction in the Instruction Register
is forced to IDCODE. The controller is guaranteed to enter Test-Logic-Reset when the
TMS input is held active for at least five clocks. The controller also enters this state
immediately when TRST# is pulled active, and automatically upon power-up of the
Pentium Pro processor. The TAP controller cannot leave this state as long as TRST# is held
active.
Run-Test/Idle: This is the idle state of the TAP controller. In this state, the contents of all
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test data registers retain their previous values.
Select-IR-Scan: This is a temporary controller state. All registers retain their previous
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values.
Capture-IR: In this state, the shift register contained in the Instruction Register loads a
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fixed value (of which the two least significant bits are "01") on the rising edge of TCK.
The parallel, latched output of the Instruction Register ("current instruction") does not
change.
Shift-IR: The shift register contained in the Instruction Register is connected between TDI
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and TDO and is shifted one stage toward its serial output on each rising edge of TCK. The
output arrives at TDO on the falling edge of TCK. The current instruction does not change.
Exit1-IR: This is a temporary state. The current instruction does not change.
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Pause-IR: Allows shifting of the instruction register to be temporarily halted. The current
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instruction does not change.
Exit2-IR: This is a temporary state. The current instruction does not change.
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Update-IR: The instruction which has been shifted into the Instruction Register is latched
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onto the parallel output of the Instruction Register on the falling edge of TCK. Once the
new instruction has been latched, it remains the current instruction until the next Update-IR
(or until the TAP controller state machine is reset).
Select-DR-Scan: This is a temporary controller state. All registers retain their previous
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values.
Capture-DR: In this state, the data register selected by the current instruction may capture
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data at its parallel inputs.
Shift-DR: The Data Register connected between TDI and TDO as a result of selection by
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the current instruction is shifted one stage toward its serial output on each rising edge of
TCK. The output arrives at TDO on the falling edge of TCK. The parallel, latched output
of the selected Data Register does not change while new data is being shifted in.
Exit1-DR: This is a temporary state. All registers retain their previous values.
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Pause-DR: Allows shifting of the selected Data Register to be temporarily halted without
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stopping TCK. All registers retain their previous values.
PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP)
10-3
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