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BUS OVERVIEW
The INIT# input signal resets all Pentium Pro processor bus agents without affecting their inter-
nal (L1 or L2) caches or their floating-point registers. Each Pentium Pro processor begins exe-
cution at the address vector as defined during power on configuration. INIT# has another
meaning on RESET#'s active to inactive transition: if INIT# is sampled active on RESET#'s ac-
tive to inactive transition, then the Pentium Pro processor executes its built-in self test (BIST).
If the FLUSH# input signal is asserted, the Pentium Pro processor bus agent writes back all in-
ternal cache lines in the Modified state (L1 and L2 caches) and invalidates all internal cache
lines (L1 and L2 caches). The flush operation puts all internal cache lines in the Invalid state.
After all lines are written back and invalidated, the Pentium Pro processor drives a special trans-
action, the Flush Acknowledge transaction, to indicate completion of the flush operation. The
FLUSH# signal has a different meaning when it is sampled asserted on the active to inactive
transition of RESET#. If FLUSH# is sampled asserted on the active to inactive transition of RE-
SET#, then the Pentium Pro processor tristates all of its outputs. This function is used during
board testing.
The Pentium Pro processor supplies a STPCLK# pin to enable the processor to enter a low pow-
er state. When STPCLK# is asserted, the Pentium Pro processor puts itself into the stop grant
state, issues a Stop Grant Acknowledge special transaction, and optionally stops providing in-
ternal clock signals to all units except the bus unit and the APIC unit. The processor continues
to snoop bus transactions while in stop grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no
effect on the bus clock.
The PICCLK and PICD[1:0]# signals support the Advanced Programmable Interrupt Controller
(APIC) interface. The PICCLK signal is an input clock to the Pentium Pro processor for syn-
chronous operation of the APIC bus. The PICD[1:0]# signals are used for bidirectional serial
message passing on the APIC bus.
LINT[1:0] are local interrupt signals, also defined by the APIC interface. In APIC disabled
mode, LINT0 defaults to INTR, a maskable interrupt request signal. LINT1 defaults to NMI, a
non-maskable interrupt. Both signals are asynchronous inputs. In the APIC enable mode, LINT0
and LINT1 are defined with the local vector table.
LINT[1:0] are also used along with the A20M# and IGNNE# signals to determine the multiplier
for the internal clock frequency as described in Chapter 9, Configuration.
3-11
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