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ELECTRICAL SPECIFICATIONS
Group Name
BPRI#, BR[3:1]# 1 , DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Input
GTL+ Output
PRDY#
GTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BR0# 1 , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#,
HITM#, LOCK#, REQ[4:0]#, RP#
3.3V Tolerant Input
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,
PWRGOOD 2 , SMI#, STPCLK#
FERR#, IERR#, THERMTRIP# 3
3.3V Tolerant Output
Clock 4
BCLK
APIC Clock 4
PICCLK
APIC I/O 4
PICD[1:0]
JTAG Input 4
TCK, TDI, TMS, TRST#
JTAG Output 4
TDO
Power/Other 5
CPUPRES#, PLL1, PLL2, TESTHI, TESTLO, UP#, V cc P, V cc S, V cc 5, VID[3:0],
V REF [7:0], V ss
NOTES:
1. The BR0# pin is the only BREQ signal that is bi-directional. The internal BREQ# signals are mapped onto
BR# pins after the agent ID is determined.
2. See PWRGOOD in Section 11.9., "PWRGOOD".
3. See THERMTRIP# in Section 11.10., "THERMTRIP#".
4. These signals are tolerant to 3.3V. Use a 150Ω pull-up resistor on PIC[1:0] and 240Ω on TDO.
5. CPUPRES# is a ground pin defined to allow a designer to detect the presence of a processor in a socket.
PLL1 & PLL2 are for decoupling the PLL (See Section 11.4.3., "Phase Lock Loop (PLL) Decoupling").
TESTHI pins should be tied to V cc P. A 10K pull-up may be used. See Section 11.11., "Unused Pins".
TESTLO pins should be tied to V ss . A 1K pull-down may be used.See Section 11.11., "Unused Pins".
UP# is an open in the Pentium
OverDrive® Processor Socket Specification .
V cc P is the primary power supply.
V cc S is the secondary power supply used by some versions of the second level cache.
V cc 5 is unused by the Pentium Pro processor and is used by the OverDrive processor for fan-sink power.
VID[3:0] lines are described in Section 11.6., "Voltage Identification".
V REF [7:0] are the reference voltage pins for the GTL+ buffers.
V ss is ground.
11-10
Table 11-2. Signal Groups
®
Pro processor and Vss in the OverDrive
Signals
®
processor See Chapter 17,
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