Simple Read Transaction; Figure 4-18. Request Initiated Data Transfer - Intel Pentium Pro Family Developer's Manual

BUS PROTOCOL
CLK
ADS#
REQa0#
HITM#
TRDY#
DBSY#
D[63:0]#
DRDY#
RS[[2:0]#

Figure 4-18. Request Initiated Data Transfer

The write transaction is driven in T1 as indicated by active ADS# and REQa0#. TRDY# is driven
3 clocks later in T4. The No Data response is driven in T7 after inactive HITM# sampled in T6
indicates no implicit writeback.
In the example, the data transfer only takes one clock, so DBSY# is not asserted.
TRDY# is observed active and DBSY# is observed inactive in T5. Therefore the data transfer
can begin in T6 as indicated by DRDY# assertion. Note that since DBSY# was also observed
inactive in T4, the same clock that TRDY# was asserted, TRDY# can be deasserted in T6. Refer
to Section 4.5.3.3., "TRDY# Deassertion Protocol" for further details.
RS[2:0]# is driven to No Data Response in T7, two clocks after the snoop phase.
4.6.2.2.

SIMPLE READ TRANSACTION

Figure 4-19 shows a simple read transaction (response-initiated data transfer). Note that the data
transfer begins in the same clock that the response is driven on RS[2:0]#.
4-34
1 2 3 4 5
A AAAAAA A A AAAAAA AA AAAAAA AA AAAAAA A A A AAAAAA A AA AA AAAA
6 7 8 9
A AAAA AA A AAAAAA AA A AAAAAA AA AA