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SIGNALS REFERENCE
A.1.5.
AP[1:0]# (I/O)
The AP[1:0]# signals are the address parity signals. They are driven by the request initiator dur-
ing the two Request Phase clocks along with ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# cov-
ers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if an even number of
covered signals are low and low if an odd number of covered signals are low. This rule allows
parity to be high when all the covered signals are high.
Provided "AERR# drive" is enabled during the power-on configuration, all bus agents begin par-
ity checking on observing active ADS# and determine if there is a parity error. On observing a
parity error on any one of the two Request Phase clocks, the bus agent asserts AERR# during
the Error Phase of the transaction.
A.1.6.
ASZ[1:0]# (I/O)
The ASZ[1:0]# signals are the memory address-space size signals. They are driven by the re-
quest initiator during the first Request Phase clock on the REQa[4:3]# pins. The ASZ[1:0]# sig-
nals are valid only when REQa[1:0]# signals equal 01B, 10B, or 11B, indicating a memory
access transaction. The ASZ[1:0]# decode is defined in Table A-1.
ASZ[1:0]#
0
0
0
1
1
x
If the memory access is within the 0-to-(4GByte -1) address space, ASZ[1:0]# must be 00B. If
the memory access is within the 4Gbyte-to-(64GByte -1) address space, ASZ[1:0]# must be
01B. All observing bus agents that support the 4Gbyte (32 bit) address space must respond to
the transaction only when ASZ[1:0]# equals 00. All observing bus agents that support the
64GByte (36- bit) address space must respond to the transaction when ASZ[1:0]# equals 00B or
01B.
A.1.7.
ATTR[7:0]# (I/O)
The ATTR[7:0]# signals are the attribute signals. They are driven by the request initiator during
the second Request Phase clock on the Ab[31:24]# pins. The ATTR[7:0]# signals are valid for
all transactions. The ATTR[7:3]# are reserved and undefined. The ATTR[2:0]# are driven based
on the Memory Range Register attributes and the Page Table attributes. Table A-2 defines
ATTR[3:0]# signals.
A-4
ASZ[1:0]#
Table A-1.
Signal Decode
0 <= A[35:3]# < 4 GB
4 GB <= A[35:3]# < 64 GB
Description
Reserved
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