Signal And Diagram Conventions - Intel Pentium Pro Family Developer's Manual

CHAPTER 3
BUS OVERVIEW
This chapter provides an overview of the Pentium Pro processor bus protocol, transactions, and
bus signals. The Pentium Pro processor supports two other synchronous busses, APIC and
JTAG. It also has PC compatibility signals and implementation specific signals. This chapter
provides a functional description of the Pentium Pro processor bus only. For the Pentium Pro
processor bus protocol specifications, see Chapter 4, Bus Protocol. For details on the Pentium
Pro processor bus transactions, see Chapter 5, Bus Transactions and Operations. For the full
Pentium Pro processor signal specifications, see Appendix A, Signals Reference and Table 11-2.
3.1.

SIGNAL AND DIAGRAM CONVENTIONS

Signal names use uppercase letters, such as ADS#. Signals in a set of related signals are distin-
guished by numeric suffixes, such as AP1 for address parity bit 1. A set of signals covering a
range of numeric suffixes is denoted as AP[1:0], for address parity bits 1 and 0. A # suffix indi-
cates that the signal is active low. A signal name without a # suffix indicates that the signal is
active high.
In many cases, signals are mapped one-to-one to physical pins with the same names. In other
cases, different signals are mapped onto the same pin. For example, this is the case with the ad-
dress pins A[35:3]#. During the first clock of the Request Phase, the address signals are driven.
The first clock is indicated by the lower case a, or just the pin name itself: Aa[35:3]#, or
A[35:3]#. During the second clock of the Request Phase other information is driven on the re-
quest pins. These signals are referenced either by their functional signal names DID[7:0]#, or by
using a lower case b with the pin name: Ab[23:16]#. Note also that several pins have configu-
ration functions at the active to inactive edge of RESET#.
The term asserted implies that a signal is driven to its active level (logic 1, FRCERR high, or
ADS# low). The term deasserted implies that a signal is driven to its inactive level (logic 0,
FRCERR low, or ADS# high). A signal driven to its active level is said to be active; a signal
driven to its inactive level is said to be inactive.
In timing diagrams, square and circle symbols indicate the clock in which particular signals of
interest are driven and sampled. The square indicates that a signal is driven in that clock. The
circle indicates that a signal is sampled in that clock.
All timing diagrams in this specification show signals as they are driven asserted or deasserted
on the Pentium Pro processor bus. There is a one-clock delay in the signal values observed by
bus agents. Any signal names that appear in lower case letters in brackets {rcnt} are internal sig-
nals only, and are not driven to the bus. Upper case letters that appear in brackets represent a
group of signals such as the Request Phase signals {REQUEST}. The timing diagrams some-
times include internal signals to indicate internal states and show how it affects external signals.
3-1